MIL-STD-1553 Implementation

• mil1553-spi

  1 25 0.0 SystemVerilog

  MIL-STD-1553 <-> SPI bridge

Something like this? https://github.com/zhelnio/mil1553-spi

• vhdl-axis-uart

  2 15 0.0 VHDL

  UART to AXI Stream interface written in VHDL

not much different than something like this: https://github.com/fcayci/vhdl-axis-uart/blob/master/rtl/uart_rx.vhd

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