vhdl-axis-uart
forth-cpu
| vhdl-axis-uart | forth-cpu | |
|---|---|---|
| 2 | 2 | |
| 15 | 315 | |
| - | - | |
| 0.0 | 2.6 | |
| over 1 year ago | about 2 years ago | |
| VHDL | VHDL | |
| MIT License | - |
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vhdl-axis-uart
- Understanding Serial port and transmission?
-
MIL-STD-1553 Implementation
not much different than something like this: https://github.com/fcayci/vhdl-axis-uart/blob/master/rtl/uart_rx.vhd
forth-cpu
-
Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
mil1553-spi - MIL-STD-1553 <-> SPI bridge
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
sdram-fpga - A FPGA core for a simple SDRAM controller.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
Arcade_Galaga - Galaga Arcade Core
Flo-Posit - Posit Arithmetic Cores generated with FloPoCo
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components