verible VS awesome-linters

I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?

BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.

You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.

https://github.com/chipsalliance/verible (may not do actual syntax checking)

You might be interested in this though.

This sounds like JavaScript: The Good Parts revisited. Agree with everything you’ve written. However, in the rare situation that one has to go down this path, a linter/static code analyzer can prove to be a life saver. Found some on this page: https://github.com/caramelomartins/awesome-linters#cc

I'll try to sum up: I believe screenwriters and story creators (including likely Mr. Whedon) have increasingly started thinking of their fiction in terms of fanfic (including crossovers, parodies and RPFs) and have increasingly been unwilling to de-fanfic them, or massage them into Hollywood's blessed format (which cannot be "linted" or "validated"), or tolerate their screenplay submissions being silently rejected without input for how they are lacking and can be improved. Furthermore, by virtue of being 21st century amateurs, they increasingly cannot be "bought" because they'd rather not accept a milliard dollar (or more) commission, than expend time, human energy, human happiness, human "love" destroying their intellectual and spiritual children.