tdt4255-chisel-intro
By PeterAaser
RISCV-FiveStage
Marginally better than redstone (by PeterAaser)
tdt4255-chisel-intro | RISCV-FiveStage | |
---|---|---|
1 | 4 | |
22 | 89 | |
- | - | |
0.0 | 0.0 | |
over 3 years ago | over 3 years ago | |
Scala | Scala | |
- | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
tdt4255-chisel-intro
Posts with mentions or reviews of tdt4255-chisel-intro.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-12.
-
Planning to develop a CPU on an FPGA. How can I program it?
I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage
RISCV-FiveStage
Posts with mentions or reviews of RISCV-FiveStage.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-15.
- Tips on building a RISC-V processor on FPGA
-
Planning to develop a CPU on an FPGA. How can I program it?
I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage
-
Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.
https://github.com/PeterAaser/RISCV-FiveStage
-
Want to get started.What to buy?
If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.
What are some alternatives?
When comparing tdt4255-chisel-intro and RISCV-FiveStage you can also consider the following projects:
cortex-m0-soft-microcontroller - Soft-microcontroller implementation of an ARM Cortex-M0
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
4-bit-CPU-Compiler - Python script to take in Pseudo assembly code and translate it into Verilog for case statements in a ROM module.
litex - Build your hardware, easily!
nmigen-tutorial - A tutorial for using nmigen
wyre - Hardware definition language that compiles to Verilog
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
riscv-tests
tdt4255-chisel-intro vs cortex-m0-soft-microcontroller
RISCV-FiveStage vs VexRiscv
tdt4255-chisel-intro vs 4-bit-CPU-Compiler
RISCV-FiveStage vs cortex-m0-soft-microcontroller
RISCV-FiveStage vs litex
RISCV-FiveStage vs nmigen-tutorial
RISCV-FiveStage vs wyre
RISCV-FiveStage vs dromajo
RISCV-FiveStage vs riscv-mini
RISCV-FiveStage vs riscv-tests
RISCV-FiveStage vs 4-bit-CPU-Compiler