systemrdl-compiler
rggen
systemrdl-compiler | rggen | |
---|---|---|
1 | 3 | |
222 | 280 | |
0.9% | 2.1% | |
7.3 | 7.7 | |
about 1 month ago | 3 months ago | |
Python | Ruby | |
MIT License | MIT License |
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systemrdl-compiler
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Tool to generate table of memory-mapped register?
Also I would recommend SystemRDL for creating a definition usable in code generators: https://github.com/SystemRDL/systemrdl-compiler
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
PeakRDL-halcpp - C++ 17 Hardware abstraction layer generator from systemrdl
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
PeakRDL-ipxact - Import and export IP-XACT XML register models
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
wavedrom - :ocean: Digital timing diagram rendering engine
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
joes-sandbox
edalize - An abstraction library for interfacing EDA tools
mrisc32 - MRSIC32 ISA documentation and development
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen