symbiflow-xc7z-automatic-tester
sphinxcontrib-hdl-diagrams
| symbiflow-xc7z-automatic-tester | sphinxcontrib-hdl-diagrams | |
|---|---|---|
| 1 | 2 | |
| 6 | 50 | |
| - | - | |
| 0.0 | 5.7 | |
| about 3 years ago | 8 months ago | |
| Python | Python | |
| ISC License | Apache License 2.0 |
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symbiflow-xc7z-automatic-tester
sphinxcontrib-hdl-diagrams
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Is there any software I can use to transform state machines in VHDL into drawings?
Well, you can convert VHDL into Verilog using Icarus Verilog, and then you can draw a logic gate diagram (.svg file) to visualize your code using this: https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
- Systemverilog / verilog functional editor not like vivado
What are some alternatives?
f4pga - FOSS Flow For FPGA
verilator - Verilator open-source SystemVerilog simulator and lint system
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
sane_tikz - Reconquer the canvas: beautiful Tikz figures without clunky Tikz code
tox
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
httpbin - HTTP Request & Response Service, written in Python + Flask.
fusesoc_template - Example of how to get started with olofk/fusesoc.
amaranth - A modern hardware definition language and toolchain based on Python
sphinx-tabs - Tabbed views for Sphinx
gdscript-docs-maker - Create documentation and class references from your Godot GDScript code
docs - Documentation site