svls
veridian
| svls | veridian | |
|---|---|---|
| 3 | 3 | |
| 411 | 104 | |
| - | - | |
| 8.1 | 4.8 | |
| 9 days ago | about 2 months ago | |
| Rust | Rust | |
| MIT License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
svls
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How to configure vim like an IDE
svls
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
I can attest first-hand to the "headache" that comes from semi company simulation environments. Not only are they horribly outdated (in Perl/Tcl), but they're different at every company you work at. There's no gold standard because the standard that these EDA companies ought to be making doesn't exist.
There needs to be an open initiative between semi companies to create a standard simulation environment -- with compilers, unit-test frameworks, and all sorts of simulation (gate-level, analog/mixed signal, emulation, etc). Hell, just give me a free IDE plugin for SystemVerilog that actually works.
This lack of a standard seems to me like the critical path in hardware design. I'm trying to support projects to fix this like SVLS (A language server for SystemVerilog: https://github.com/dalance/svls) but these are all hard problems to solve. This industry is relatively niche and doesn't seem to have many engineers interested in FOSS.
veridian
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How to configure vim like an IDE
SystemVerilog
- Tools like Scitools Understand but support Verilog
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Are you using tree-sitter via nvim-treesitter plugin?
Neovim's native LSP support with Slang and/or Verible + https://github.com/vivekmalneedi/veridian
What are some alternatives?
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
verilog_systemverilog.vim - Verilog/SystemVerilog Syntax and Omni-completion
texlab - An implementation of the Language Server Protocol for LaTeX
hdl_checker - Repurposing existing HDL tools to help writing better code
Verilog.jl - Verilog for Julia
circt - Circuit IR Compilers and Tools
svlint - SystemVerilog linter
RecursiveFactorization.jl
iverilog - Icarus Verilog
Modia.jl - Modeling and simulation of multidomain engineering systems
slang - SystemVerilog compiler and language services