svls
Verilog.jl
svls | Verilog.jl | |
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3 | 2 | |
411 | 46 | |
- | - | |
8.1 | 0.0 | |
9 days ago | about 7 years ago | |
Rust | Julia | |
MIT License | GNU General Public License v3.0 or later |
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svls
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How to configure vim like an IDE
svls
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
I can attest first-hand to the "headache" that comes from semi company simulation environments. Not only are they horribly outdated (in Perl/Tcl), but they're different at every company you work at. There's no gold standard because the standard that these EDA companies ought to be making doesn't exist.
There needs to be an open initiative between semi companies to create a standard simulation environment -- with compilers, unit-test frameworks, and all sorts of simulation (gate-level, analog/mixed signal, emulation, etc). Hell, just give me a free IDE plugin for SystemVerilog that actually works.
This lack of a standard seems to me like the critical path in hardware design. I'm trying to support projects to fix this like SVLS (A language server for SystemVerilog: https://github.com/dalance/svls) but these are all hard problems to solve. This industry is relatively niche and doesn't seem to have many engineers interested in FOSS.
Verilog.jl
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Compiling Code into Silicon
It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.
https://github.com/interplanetary-robot/Verilog.jl
Of course, gaining traction on something like this is tricky.
I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl
What are some alternatives?
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
veridian - A SystemVerilog Language Server
Octavian.jl - Multi-threaded BLAS-like library that provides pure Julia matrix multiplication
texlab - An implementation of the Language Server Protocol for LaTeX
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
circt - Circuit IR Compilers and Tools
Modia.jl - Modeling and simulation of multidomain engineering systems
RecursiveFactorization.jl
Automa.jl - A julia code generator for regular expressions
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen