simple-riscv VS fpu

Compare simple-riscv vs fpu and see what are their differences.

simple-riscv

A simple three-stage RISC-V CPU (by hamsternz)
Fpga risc-v Vhdl
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fpu

IEEE 754 floating point library in system-verilog and vhdl (by taneroksuz)
Fpu Hardware risc-v system-verilog Vhdl Verilog Fpga
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simple-riscv fpu
5 1
19 46
- -
2.7 6.1
about 3 years ago 2 months ago
VHDL VHDL
MIT License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

simple-riscv

Posts with mentions or reviews of simple-riscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-11-23.

fpu

Posts with mentions or reviews of fpu. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-08.
  • High level floating point arithmetic in vhdl
    3 projects | /r/FPGA | 8 Aug 2022
    Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.

What are some alternatives?

When comparing simple-riscv and fpu you can also consider the following projects:

neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

riscv-tests

fpu-sp - IEEE 754 floating point library in system-verilog and vhdl

riscv-formal - RISC-V Formal Verification Framework

uart-for-fpga - Simple UART controller for FPGA written in VHDL

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

or1200 - OpenRISC 1200 implementation

Cores-VeeR-EH1 - VeeR EH1 core

spi-fpga - SPI master and SPI slave for FPGA written in VHDL

Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.

VHDL-Guide - VHDL Guide

simple-riscv vs neo430 fpu vs neorv32-setups simple-riscv vs riscv-tests fpu vs fpu-sp simple-riscv vs riscv-formal fpu vs uart-for-fpga simple-riscv vs rp32 fpu vs or1200 simple-riscv vs Cores-VeeR-EH1 fpu vs spi-fpga fpu vs Hastlayer-SDK fpu vs VHDL-Guide