riscv-simple-sv
A simple RISC V core for teaching (by tilk)
gdb-stub
gdb-proxy implementation for bonfire (by bonfireprocessor)
| riscv-simple-sv | gdb-stub | |
|---|---|---|
| 2 | 1 | |
| 145 | 0 | |
| - | - | |
| 0.0 | 3.7 | |
| over 2 years ago | 10 months ago | |
| SystemVerilog | C | |
| BSD 3-clause "New" or "Revised" License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-simple-sv
Posts with mentions or reviews of riscv-simple-sv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-10.
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Simple CPU cores to study?
I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
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Need help in CPU design
I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?
gdb-stub
Posts with mentions or reviews of gdb-stub.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-03-22.
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Need help in CPU design
Regarding debug, very few open source cores support anything approaching the kind of debug interface you would find on a microcontroller or vendor core (breakpoints, single stepping and memory viewers). Supporting these features involves considerable extra hardware and some special software to interface with GDB, called a GDB stub. The Bonfire CPU has support for a GDB stub but I've never tried it.
What are some alternatives?
When comparing riscv-simple-sv and gdb-stub you can also consider the following projects:
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv_verilator_model - RISCV model for Verilator/FPGA targets
picoMIPS - picoMIPS processor doing affine transformation
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
rhd - Tiny 16-bit RISC Core
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40
riscv-simple-sv vs cv32e40p
gdb-stub vs neorv32
riscv-simple-sv vs scr1
gdb-stub vs riscv_verilator_model
riscv-simple-sv vs picoMIPS
gdb-stub vs picoMIPS
riscv-simple-sv vs neorv32
riscv-simple-sv vs VeriGPU
riscv-simple-sv vs rhd
riscv-simple-sv vs FPGA-Video-Processing
riscv-simple-sv vs ulm-on-ice