riscv-boom
sandsifter
Our great sponsors
riscv-boom | sandsifter | |
---|---|---|
12 | 15 | |
1,593 | 4,826 | |
3.0% | - | |
7.2 | 0.0 | |
about 1 month ago | 2 months ago | |
Scala | Python | |
BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
-
Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
-
In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
-
PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
-
Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
-
The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
-
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
-
Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
sandsifter
- Cascade: CPU Fuzzing via Intricate Program Generation
- Sandsifter: The x86 Processor Fuzzer
- How would undocummented, private ISA extensions work in Linux-based systems?
- I found a bug in Intel Skylake processors
-
Is there any opensource switch brand?
This has some background.
- Clever Hack Finds Mystery CPU Instructions
- Sandsifter – The x86 Processor Fuzzer
-
The Cursed Computer Iceberg Meme
sandsifter
-
Speculating the Entire x86-64 Instruction Set in Seconds with One Weird Trick
This is a really clever technique! I was impressed by sandsifter[1] when it originally came out, and this seems an awful lot faster and less prone to false negatives (since it's purely speculative and doesn't require sandsifter's `#PF` hack).
At the risk of unwarranted self-promotion: the other side of this equation is fidelity in software instruction set decoders. x86's massive size and layers of historical complexity make it among the most difficult instruction formats to accurately decode; I've spent a good part of the last two years working on a fuzzer that's discovered thousands of bugs in various popular x86 decoders[2][3].
[1]: https://github.com/xoreaxeaxeax/sandsifter
[2]: https://github.com/trailofbits/mishegos
[3]: https://ww.easychair.org/publications/preprint_download/1LHr
-
Capstone Disassembler Framework
Idea:
If any assembler/disassembler author/team out there wants to produce an assembler/disassembler which is authoritative (difficult to do on x86, because there are so many different possible combinations of instruction encoding, https://github.com/xoreaxeaxeax/sandsifter : "Typically, several million undocumented instructions on your processor will be found, but these generally fall into a small number of different groups.") -- then what they'd do is to create a third program -- which "pits" the output of Assembler A vs. Assembler B, Disassembler A vs. Disassembler B...
That is, between any two assemblers (for the same CPU architecture/instruction set), or any two disassemblers, where are the anomalies?
If we think about an assembler as a simple function, y=f(x), that is, I give it a string of ascii bytes as input (x), and I get a string (1..n) binary bytes as output (y),
What are some alternatives?
rocket-chip - Rocket Chip Generator
trapcc - Computing with traps
openc910 - OpenXuantie - OpenC910 Core
tatradas - Disassembler for x86 executables (16-bit and 32-bit) which supports PE, NE, MZ, COM and ELF file formats
XiangShan - Open-source high-performance RISC-V processor
fuzzing - Tutorials, examples, discussions, research proposals, and other resources related to fuzzing
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
lazarus - Free Pascal Lazarus Project - Sync'ed with Lazarus SubVersion trunk every 15 minutes
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]
Cores-VeeR-EL2 - VeeR EL2 Core
docs - Hardware and software docs / wiki