riscv-boom
riscv-gnu-toolchain
riscv-boom | riscv-gnu-toolchain | |
---|---|---|
12 | 35 | |
1,599 | 3,168 | |
1.9% | 3.7% | |
7.2 | 8.2 | |
about 2 months ago | 6 days ago | |
Scala | C | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
riscv-gnu-toolchain
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
> no absurdely and grotesquely massive and complex compilers anywhere
Absence of evidence is not evidence of absence, and anyway there's not even an absence: https://github.com/riscv-collab/riscv-gnu-toolchain https://llvm.org/docs/RISCVUsage.html
> feature creeps on computer language syntax nowhere to be found
At least one of us is very confused, and in case it's me, how do language details matter to RISC-V?
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Help trying to build for riscv64gc-unknown-linux-musl
I then looked at the .cargo/config.toml provided by the guide and saw that it wasn't actually statically compiling the code. After a bit of tinkering and building my own toolchain from here, I ended up with this config.toml file:
- GNU toolchain for RISC-V including GCC
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Building a toolchain suitable for compiling V extension code
b) collabriscv - essentially gcc 12.2 + binutils master/2.40 as per https://github.com/riscv-collab/riscv-gnu-toolchain
- How do i specify vendor name while building the GNU toolchain?
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GCC 13 Adds RISC-V T-Head Vendor Extension Collection
Or would it be better to take what is in https://github.com/riscv-collab/riscv-gnu-toolchain which is gcc 12.2 and start from there?
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How to build toolchain with Zbs extension?
I'm not able to build https://github.com/riscv-collab/riscv-gnu-toolchain.git like this:
What are some alternatives?
rocket-chip - Rocket Chip Generator
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
openc910 - OpenXuantie - OpenC910 Core
risc-v-examples - RISC-V examples for GD32V, K210, and QEMU
XiangShan - Open-source high-performance RISC-V processor
rvv-llvm - This repository is outdated, support for RISC-V is now developed in upstream LLVM
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
buildroot - Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
freedom-tools - Tools for SiFive's Freedom Platform
Cores-VeeR-EL2 - VeeR EL2 Core
xv6-riscv - Xv6 for RISC-V