verilator
| rhrq-riscv-extensions | verilator | |
|---|---|---|
| 1 | 11 | |
| 1 | 2,118 | |
| - | 3.0% | |
| 7.5 | 9.8 | |
| 7 months ago | 6 days ago | |
| C++ | ||
| GNU General Public License v3.0 only | GNU Lesser General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rhrq-riscv-extensions
verilator
-
What's new for RISC-V in LLVM 17
You may want to check out Verilator:
https://verilator.org/
- How to run & simulate system verilog files on VScode?
-
Choosing a Verification Methodology
relevant issue
-
Designing Billions of Circuits with Code
One notable exception is Verilator which is growing fast and competes welll with commercial Verilog simulators (https://github.com/verilator/verilator)
-
Error when running cocotb using cocotb-test
It is 4.106, check https://github.com/verilator/verilator/issues/2778 for more details.
-
Verilator: Suggestions for verification framework?
Yeah, there is currently a bug and only one specific version of verilator works with cocotb (4.106). Hopefully it will be fixed soon. Go make noise here: https://github.com/verilator/verilator/issues/2778.
-
Vitis HLS and Verilator
Okay, made it. Problem is, that my account is flagged as soon as I created it, I am marked as "spammy", and my "comments will only be shown in staff mode". https://github.com/verilator/verilator/issues/3159
- Attention to everyone that is using Verilator and C++! DO NOT update your GCC Package to version 11.1, because it will cause Verilator's object files to fail to compile properly. I have been dealing with this issue for four days straight and have only now found the solution. You have been warned.
-
Systemverilog / verilog functional editor not like vivado
If you will help me with systemverilog black box discusion (I have very low systemverilog experience) and verilator will get update then I will upload on github plugin to Sublime Text which lint whole file every time when you stop typing. Currently I have plugin based on Vivado's compiler, but compilation of simple verilog file takes 1'400ms...
-
eProcessor is a project that will create a open source RISC-V core for High Performance Computing (HPC)
You have verilator which is a open source simulator , so it is feasible that a "user" could fix a bug or implement a feature (i does not have to be some individual, a business or a university could do it to).
What are some alternatives?
wavedrom - :ocean: Digital timing diagram rendering engine
HLS-Tiny-Tutorials - This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
signalflip-js - verilator testbench w/ Javascript using N-API
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
buildit - Online demo without installing at - https://buildit.so/tryit
mewa - Compiler-compiler for writing compiler frontends with Lua
naja-verilog - A standalone structural (gate-level) verilog parser
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
naja - Structural Netlist API (and more) for EDA post synthesis flow development