rggen
| rggen | rggen-sample | |
|---|---|---|
| 3 | 1 | |
| 279 | 8 | |
| 1.8% | - | |
| 7.7 | 6.2 | |
| 3 months ago | 3 months ago | |
| Ruby | VHDL | |
| MIT License | MIT License |
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rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
rggen-sample
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
rggen-c-header - C header file writer plugin for RgGen
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
PeakRDL-ipxact - Import and export IP-XACT XML register models
edalize - An abstraction library for interfacing EDA tools
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
veryl - Veryl: A Modern Hardware Description Language
systemrdl-compiler - SystemRDL 2.0 language compiler front-end
rggen-verilog-rtl - Common Verilog RTL modules for RgGen