rapcores | serv | |
---|---|---|
3 | 20 | |
22 | 1,254 | |
- | - | |
0.0 | 7.6 | |
over 2 years ago | 23 days ago | |
Verilog | Verilog | |
ISC License | ISC License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rapcores
Posts with mentions or reviews of rapcores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-21.
-
FPGA development automation practices
Our project is: https://github.com/RAPcores/rapcores I have a draft article about the tools we use, but it is several months old now. We are about one year into the project, and I am amazed how every month some new tooling seems to pop up that solves some problem.
- PWM for BLDC motor RPM control on Arty A7 100T
-
Lessons learned while building an ASIC design
Really good write up. We recently did a tape out as well and had similar learnings :) Would have definitely been nice to see this a few months ago. As part of our CI we have started parsing with Yosys, Verilator, and IVerilog. I cannot recommend this enough. There is a perfectly capable subset of verilog dialect amongst all three, and gives you nice protability amongst FOSS toolchains. Running parsing checks is a great way to lint/sanity check things. We also put together a simple script to check register initializations that has been really helpful also: https://github.com/RAPcores/rapcores/blob/main/etc/reginit.sh
serv
Posts with mentions or reviews of serv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-30.
-
RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
-
Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
-
Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
-
I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
-
RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know