python-fpga-interchange
f4pga-examples
| python-fpga-interchange | f4pga-examples | |
|---|---|---|
| 1 | 1 | |
| 39 | 261 | |
| - | 1.1% | |
| 0.0 | 4.3 | |
| over 1 year ago | about 2 months ago | |
| Python | Verilog | |
| ISC License | Apache License 2.0 |
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python-fpga-interchange
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FPGA Interchange format to enable interoperable FPGA tooling
Or BLIF or EBLIF (already used by the verilog-to-routing flow). But no, let's invent yet another netlist format.
The fact that all of these existing formats are all named "xxx logic interchange format" should give you an idea what will happen to this new "interchange format".
From what I gather ( https://github.com/SymbiFlow/python-fpga-interchange/blob/ma... ) , the new format is basically the existing Yosys/nextpnr JSON format except dumped as a Cap'n Proto binary file.
I am absolutely not impressed.
I guess the meat here is on the universal device resources format, but this is not cool anyway.
f4pga-examples
What are some alternatives?
firrtl - Flexible Intermediate Representation for RTL
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
netlistsvg - draws an SVG schematic from a JSON netlist
zipcpu - A small, light weight, RISC CPU soft core
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
prjxray - Documenting the Xilinx 7-series bit-stream format.
ideas - Random ideas and interesting ideas for things we hope to eventually do.
f4pga - FOSS Flow For FPGA
chisel - Chisel: A Modern Hardware Design Language
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
hdl - HDL libraries and projects