prjxray
sphinxcontrib-hdl-diagrams
| prjxray | sphinxcontrib-hdl-diagrams | |
|---|---|---|
| 8 | 2 | |
| 736 | 50 | |
| 0.7% | - | |
| 8.4 | 5.7 | |
| 11 days ago | 7 months ago | |
| Python | Python | |
| ISC License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
prjxray
- AMD Proposes an FPGA Subsystem User-Space Interface for Linux
- OpenPOWER Foundation Demoes the LibreBMC Power-Based Open-Source BMC
-
Using FPGAs for CyberSecurity/Cryptography.
There are many applications to FPGA security. You could use Project X-Ray to reverse engineer and edit a bitstream. You could learn how to use encrypted bitstreams to prevent someone from reverse engineering and editing your own bitstream. You could perform a side channel attack on an FPGA.
-
NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop (2019)
A bit of a nitpick - LiteX still needs Vivado installed for now for 7 series FPGAs. There's a project that's very far along in reverse engineering the Xilinx bitstream (https://github.com/f4pga/prjxray), but it's still missing many features (PCIe, SERDES, etc.).
-
Partial reconfiguration safety problems
this information is not difficult to extract. maybe make a donation to https://github.com/f4pga/prjxray or appeal to their vanity. they can probably write such a script in an hour or two.
- Symbiflow: The GCC of the FPGA World
-
The J1 Forth CPU
Here is a project to reverse engineer the Xilinx series 7 FPGAs to be able to target them with open source tools:
https://github.com/SymbiFlow/prjxray
sphinxcontrib-hdl-diagrams
-
Is there any software I can use to transform state machines in VHDL into drawings?
Well, you can convert VHDL into Verilog using Icarus Verilog, and then you can draw a logic gate diagram (.svg file) to visualize your code using this: https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
- Systemverilog / verilog functional editor not like vivado
What are some alternatives?
openFPGALoader - Universal utility for programming FPGA
verilator - Verilator open-source SystemVerilog simulator and lint system
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
sane_tikz - Reconquer the canvas: beautiful Tikz figures without clunky Tikz code
FPGA-Ping-Pong-game - Simple Ping Pong game on Xilinx Spartan 3E
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
f4pga - FOSS Flow For FPGA
fusesoc_template - Example of how to get started with olofk/fusesoc.
litex - Build your hardware, easily!
amaranth - A modern hardware definition language and toolchain based on Python
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
sphinx-tabs - Tabbed views for Sphinx