picorv32
awesome-riscv
picorv32 | awesome-riscv | |
---|---|---|
16 | 5 | |
2,805 | 116 | |
2.7% | - | |
5.2 | 0.0 | |
about 2 months ago | about 1 year ago | |
Verilog | ||
ISC License | - |
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picorv32
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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SPI PROTOCOL in FPGA
In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v
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How many gates does a decent risc-v implementation take?
The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.
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Open-source RISC-V CPU projects for contribution
Picorv32: https://github.com/YosysHQ/picorv32
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We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
picorv32 is written in Verilog.
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
That is, reducing the number of LUT required to implement a CPU of a given ISA.
A basic RV32 CPU is down to 500-700 LUT.
https://github.com/YosysHQ/picorv32
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Designing a reasonable memory interface
I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.
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Risc-v rv32i softcore processor for Zybo-z7-10
Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32
awesome-riscv
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Rise: RISC-V Software Ecosystem – Linux Foundation Project
Github seems like a good option for this (or codeberg), creating something like awesome risc-v where other people can make suggestions and improvements.
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How many gates does a decent risc-v implementation take?
The lists out there are out of date, but this isn't a bad place to start.
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Yeah, RISC-V Is Actually a Good Design
In general, I've been seeing quite a few interesting open-source implementations; what RISC-V has brought to the table is a community and an ISA that open CPU implementors can get behind, and vice versa, which has led to a lot of advancements in open CPU development.
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What is needed for a processor other than instruction sets?
If you'd like to learn first-hand, why not look at a few open-source implementations for yourself? I think that's one of the incidental benefits of RV - people implementing their own FOSS cores with a shared instruction set!
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Russian Company Develops 32-Bit RISC-V Microcontroller
RISC-V is about to take off! https://github.com/drom/awesome-riscv
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
openc910 - OpenXuantie - OpenC910 Core
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
JuiceVm - The juice virtual machine was born in 2020, with the goal of realizing the smallest virtual machine of RISC-V that can run the latest kernel mainline. At the beginning of the design, it runs on a platform with only 100 KB of RAM, which does not exceed the number of C99. Three-party dependence.
rocket-chip - Rocket Chip Generator
valgrind-riscv64 - Valgrind with support for the RISCV64/Linux platform.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
GCC-Cross-Compiler - These are gcc cross compiler tools.
wd65c02 - Cycle accurate FPGA implementation of various 6502 CPU variants
.NET Runtime - .NET is a cross-platform runtime for cloud, mobile, desktop, and IoT apps.
Projects - Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8
awesome-mango-pi-mq-pro - A curated list of awesome MangoPi MQ-Pro images, tools and resources