open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools (by Obijuan)
rapcores
Robotic Application Processor (by RAPcores)
open-fpga-verilog-tutorial | rapcores | |
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3 | 3 | |
743 | 22 | |
- | - | |
0.0 | 0.0 | |
about 4 years ago | over 2 years ago | |
Verilog | Verilog | |
GNU General Public License v3.0 only | ISC License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
open-fpga-verilog-tutorial
Posts with mentions or reviews of open-fpga-verilog-tutorial.
We have used some of these posts to build our list of alternatives
and similar projects.
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FPGA for beginners?
The toolchain is called Icestorm, main tool is yosys, most information will be in English. I started with this tutorials here (also in English) https://github.com/Obijuan/open-fpga-verilog-tutorial. Then I used books to learn more on the basics of cpu design in verilog (which can also found online). Obijuan is a Spanish profesor teaching digital electronics in university, he lead the development of a graphical user interface to generate verilog based on a blocks UI, which helps design circuits when you are starting, but unfortunately I believe all his videos are in Spanish, I'd suggest you give it a try even if you don't understand English, as the material available (wiki and videos) is very good. Look for "fpgawars jedi academy " and IceStudio (the tool). But in the end, I personally felt limited by the GUI tool (which was still under heavy development at the time) and went straight to code the verilog code by hand (which obviously is more flexible). Anyway I feel there are not that many pattern to know.
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What's the difference between FPGA, RISC-V, Arduino?
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
- Digital Design for FPGAs, with free tools
rapcores
Posts with mentions or reviews of rapcores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-21.
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FPGA development automation practices
Our project is: https://github.com/RAPcores/rapcores I have a draft article about the tools we use, but it is several months old now. We are about one year into the project, and I am amazed how every month some new tooling seems to pop up that solves some problem.
- PWM for BLDC motor RPM control on Arty A7 100T
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Lessons learned while building an ASIC design
Really good write up. We recently did a tape out as well and had similar learnings :) Would have definitely been nice to see this a few months ago. As part of our CI we have started parsing with Yosys, Verilator, and IVerilog. I cannot recommend this enough. There is a perfectly capable subset of verilog dialect amongst all three, and gives you nice protability amongst FOSS toolchains. Running parsing checks is a great way to lint/sanity check things. We also put together a simple script to check register initializations that has been really helpful also: https://github.com/RAPcores/rapcores/blob/main/etc/reginit.sh
What are some alternatives?
When comparing open-fpga-verilog-tutorial and rapcores you can also consider the following projects:
icestudio - :snowflake: Visual editor for open FPGA boards
wb2axip - Bus bridges and other odds and ends
apio - :seedling: Open source ecosystem for open FPGA boards
riscv - RISC-V CPU Core (RV32IM)
uhd - The USRP™ Hardware Driver Repository
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.
hdl - HDL libraries and projects
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
zipcpu - A small, light weight, RISC CPU soft core
serv - SERV - The SErial RISC-V CPU
open-fpga-verilog-tutorial vs icestudio
rapcores vs wb2axip
open-fpga-verilog-tutorial vs apio
rapcores vs riscv
open-fpga-verilog-tutorial vs uhd
rapcores vs darkriscv
open-fpga-verilog-tutorial vs FPGA_Asynchronous_FIFO
rapcores vs hdl
open-fpga-verilog-tutorial vs NTHU-ICLAB
rapcores vs zipcpu
open-fpga-verilog-tutorial vs darkriscv
rapcores vs serv