open-fpga-verilog-tutorial
psram-tang-nano-9k
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open-fpga-verilog-tutorial | psram-tang-nano-9k | |
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Verilog | Verilog | |
GNU General Public License v3.0 only | Apache License 2.0 |
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open-fpga-verilog-tutorial
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FPGA for beginners?
The toolchain is called Icestorm, main tool is yosys, most information will be in English. I started with this tutorials here (also in English) https://github.com/Obijuan/open-fpga-verilog-tutorial. Then I used books to learn more on the basics of cpu design in verilog (which can also found online). Obijuan is a Spanish profesor teaching digital electronics in university, he lead the development of a graphical user interface to generate verilog based on a blocks UI, which helps design circuits when you are starting, but unfortunately I believe all his videos are in Spanish, I'd suggest you give it a try even if you don't understand English, as the material available (wiki and videos) is very good. Look for "fpgawars jedi academy " and IceStudio (the tool). But in the end, I personally felt limited by the GUI tool (which was still under heavy development at the time) and went straight to code the verilog code by hand (which obviously is more flexible). Anyway I feel there are not that many pattern to know.
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What's the difference between FPGA, RISC-V, Arduino?
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
- Digital Design for FPGAs, with free tools
psram-tang-nano-9k
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Using the OSS PsramController with both dies
See my reply here: https://github.com/zf3/psram-tang-nano-9k/issues/6
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Open HyperRAM interface for Nano 9K
I added a note about his to the controller's readme. "Quick discussion about going above 83Mhz".
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Gowin: PSRAM unusable on Tang Nano 9K: stuck in Wrapped Burst mode in read and write operations (HyperRAM on Tang Nano 4K works OK with Linear Bursts)
Another difference that I find in that W955D8MBYA data sheet compared to W955N8MBY, is that W955D8MBYA does not mention anywhere that differential signaling would be optional: but instead it marks it as required. If that is the case, then the question for Best Behavior(tm) of how to properly feed it LVDS does rise again. ( https://github.com/zf3/psram-tang-nano-9k/issues/1 )
- An open source PSRAM/HyperRAM controller for Tang Nano 9k
What are some alternatives?
icestudio - :snowflake: Visual editor for open FPGA boards
uhd - The USRP™ Hardware Driver Repository
apio - :seedling: Open source ecosystem for open FPGA boards
nano4k_hdmi_tx - Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K
serv - SERV - The SErial RISC-V CPU
FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
corundum - Open source FPGA-based NIC and platform for in-network compute
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv - RISC-V CPU Core (RV32IM)