ndk-app-minimal
Minimal Application based on Network Development Kit (NDK) for FPGA cards (by CESNET)
neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). (by stnolting)
| ndk-app-minimal | neoTRNG | |
|---|---|---|
| 4 | 10 | |
| 23 | 152 | |
| - | - | |
| 8.2 | 7.5 | |
| 17 days ago | about 1 month ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ndk-app-minimal
Posts with mentions or reviews of ndk-app-minimal.
We have used some of these posts to build our list of alternatives
and similar projects.
-
A simple high-throughput open-source packet generator
as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.
-
Xilinx alternatives??
We have few Intel Agilex I-Series FPGA boards in our lab. It can do 400G Ethernet 8x56Gb or 4x112Gb (F-Tile), PCIe Gen5 x16 (R-Tile) and CXL IP is for a fee, I think. You can find an example of using F/R-Tile in our open-source NDK: https://github.com/CESNET/ndk-app-minimal
- The Network Development Kit for FPGA cards in version 0.3.1 released
- The Network Development Kit for FPGA cards released as open-source
neoTRNG
Posts with mentions or reviews of neoTRNG.
We have used some of these posts to build our list of alternatives
and similar projects.
- A really tiny and platform-independent true random number generator for FPGAs and ASICs
- Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
-
Synthesizable LFSR counter (feedback 16,13)
This TRNG (VHDL) provides some kind of "imulation mode where the entropy source is replaced by a LFSR. When simulated, the testbench prints the random data to the simulator console. Maybe this can help as starting point.
- A tiny and platform-agnostic TRUE random number generator for any FPGA
- A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- A Tiny and Platform-Independent True Random Number Generator for any FPGA.
What are some alternatives?
When comparing ndk-app-minimal and neoTRNG you can also consider the following projects:
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.