mrisc32 VS mrisc32-a1

Compare mrisc32 vs mrisc32-a1 and see what are their differences.

mrisc32

MRSIC32 ISA documentation and development (by mrisc32)

mrisc32-a1

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA (by mrisc32)
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mrisc32 mrisc32-a1
3 3
90 22
- -
10.0 0.0
9 months ago 9 months ago
TeX VHDL
Creative Commons Attribution Share Alike 4.0 -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

mrisc32

Posts with mentions or reviews of mrisc32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-17.
  • Is x86 really that bad?
    2 projects | /r/asm | 17 Feb 2023
    For my own FPGA computer project (with my on ISA, MRISC32) I use a mix of C++, C and assembler (in that order) for system code (e.g. the ROM firmware, boot-loader, program startup code, system libraries etc).
  • Tool to generate table of memory-mapped register?
    5 projects | /r/FPGA | 11 Feb 2023
    I use it extensively in my MRISC32 ISA manual (much of which is generated by a Python script): https://github.com/mrisc32/mrisc32
  • What OS do you use for development (and professional) purposes?
    1 project | /r/FPGA | 11 Jan 2023
    Third, I find it easier to make hybrid authored + generated documentation with text based documentation tools. For instance the MRISC32 Instruction Set Manual is written in LaTeX, where most of the documentation is generated by Python scripts that read CPU instruction meta data from YAML files (see https://github.com/mrisc32/mrisc32 ).

mrisc32-a1

Posts with mentions or reviews of mrisc32-a1. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-10.
  • Got any good reads on floating point math design?
    4 projects | /r/FPGA | 10 Jun 2022
    I saw a particularly efficient VHDL implementation in the mrisc32-a1, though this is lacking support for rounding modes. Together with the rest of the processor this is a very interesting project, I hope that the author progresses it further.
  • Find the leading '0' Verilog question
    1 project | /r/FPGA | 24 May 2022
    Here is a different more logic gate:ish solution (in VHDL): https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/alu/clz32.vhd
  • Floating point unit in systemc
    1 project | /r/FPGA | 22 Dec 2020
    In my VHDL implementation I use the same iterative divider for integer and for floating-point: https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/muldiv/div_impl.vhd

What are some alternatives?

When comparing mrisc32 and mrisc32-a1 you can also consider the following projects:

PeakRDL-pdf - Converts the SystemRDL data into pdf Register specification

cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

wavedrom - :ocean: Digital timing diagram rendering engine

fpu-sp - IEEE 754 floating point library in system-verilog and vhdl

mrisc32-gnu-toolchain - A top level repository for building the MRISC32 GNU toolchain

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

systemrdl-compiler - SystemRDL 2.0 language compiler front-end

lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

joes-sandbox

forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL

hlsVHDL_floating_point