icestorm
chisel
icestorm | chisel | |
---|---|---|
7 | 25 | |
952 | 3,738 | |
1.2% | 1.7% | |
0.0 | 9.7 | |
24 days ago | 6 days ago | |
Python | Scala | |
ISC License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
icestorm
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Framework Laptop feature requests – RISC-V Mainboard
I'd also vote for an FPGA Mainboard, ideally Lattice, ideally iCE40, and ideally compatible with Project IceStorm (Yosys, Arachne-pnr, and IceStorm) open source tools:
https://github.com/YosysHQ/icestorm
Think something similar to MiSTer FPGA -- but in a laptop form factor, and able to run all sorts of "soft" CPUs, i.e.:
https://opencores.org/projects?expanded=Processor
- Are there any resources detailing how synthesis happens for a particular FPGA?
- Building the SAP-2 on an FPGA
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Learning Verilog and FPGA
As others have already mentioned the Lattice ice40 family is supported by OSS chains through project icestorm [0].
There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:
- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/
- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...
[0] https://github.com/YosysHQ/icestorm
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Thoughts on OSFPGA?
You know the best part about Lattice FPGAs? The iCE40 bitstream has been reverse-engineered. As a result, you can delete Diamond and use a completely open-source toolchain instead. It's so much cleaner, easier, and less bloated that it just shows how awful all the vendor tools have gotten.
- Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
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J2 open processor: an open source processor using the SuperH ISA
>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.
>Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot.
Nice!
But, it would be an additional serious "would be nice" -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain:
https://www.latticesemi.com/Products
http://www.clifford.at/icestorm/
https://github.com/YosysHQ/icestorm
chisel
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Calyx: Intermediate Language for Hardware Accelerators
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
- Chisel: A Modern Hardware Design Language
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I may be creating an abomination
Inspired by Scala. Which can do a whole lot more, and worse. The currently biggest competitor to decades old hardware description languages is a Scala DSL.
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An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Already mentioned Chisel: https://www.chisel-lang.org/
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Trying to learn and work with FPGAs
I'm also a hobbyist. There are a number of alternative HDLs out there, and as hobbyists we can deviate more from the mainstream of (System)Verilog and VHDL if we desire, though you'll still need to be able to read them. In the past I've done Verilog, but lately I've been using SpinalHDL and have been really enjoying it. Its close relative Chisel also makes appearances in the RISC-V space.
- Alternate HDL language and Physical Design/EDA tools?
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Learning Verilog and FPGA
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
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If you keep clicking "Give 15 seconds" on Lichess, eventually it overflows to a negative number and you win
But some go further and ask "what if when we add a soldering station on top of it?"
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What universities have good PhD programmes in digital design?
In recent years Chisel HDL, RISC V, and SiFive came out of their architecture group, to name a few.
What are some alternatives?
ghdl-yosys-plugin - VHDL synthesis (based on ghdl)
SpinalHDL - Scala based HDL
apio - :seedling: Open source ecosystem for open FPGA boards
myhdl - The MyHDL development repository
prince - The Prince lightweight block cipher in Verilog.
amaranth - A modern hardware definition language and toolchain based on Python
dbus_ti_link_uart_verilog - Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
abc - ABC: System for Sequential Logic Synthesis and Formal Verification
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
bsc - Bluespec Compiler (BSC)