hVHDL_gigabit_ethernet
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers. (by hVHDL)
liteeth
Small footprint and configurable Ethernet core (by enjoy-digital)
| hVHDL_gigabit_ethernet | liteeth | |
|---|---|---|
| 1 | 2 | |
| 10 | 191 | |
| - | - | |
| 7.4 | 8.9 | |
| 9 months ago | 21 days ago | |
| VHDL | Python | |
| MIT License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hVHDL_gigabit_ethernet
Posts with mentions or reviews of hVHDL_gigabit_ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
liteeth
Posts with mentions or reviews of liteeth.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
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Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
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Ethernet 1G-over RGMII lattice
You can get some hints from LiteEth’s vendor-free ECP5 RGMII PHY: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/ecp5rgmii.py
What are some alternatives?
When comparing hVHDL_gigabit_ethernet and liteeth you can also consider the following projects:
ethernet - ethernet experiments on the ECP5-versa
verilog-ethernet - Verilog Ethernet components for FPGA implementation
Verilog_UDP_TCP - Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
axis_udp - This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
OS-X-LibMPSSE-SPI
ethernet_mac - Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
hVHDL_gigabit_ethernet vs ethernet
liteeth vs verilog-ethernet
hVHDL_gigabit_ethernet vs Verilog_UDP_TCP
liteeth vs axis_udp
hVHDL_gigabit_ethernet vs OS-X-LibMPSSE-SPI
liteeth vs ethernet
hVHDL_gigabit_ethernet vs verilog-ethernet
liteeth vs Verilog_UDP_TCP
hVHDL_gigabit_ethernet vs axis_udp
liteeth vs ethernet_mac
liteeth vs OS-X-LibMPSSE-SPI