hVHDL_gigabit_ethernet
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers. (by hVHDL)
| hVHDL_gigabit_ethernet | OS-X-LibMPSSE-SPI | |
|---|---|---|
| 1 | 1 | |
| 10 | 4 | |
| - | - | |
| 7.4 | 0.0 | |
| 9 months ago | over 2 years ago | |
| VHDL | C | |
| MIT License | - |
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Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hVHDL_gigabit_ethernet
Posts with mentions or reviews of hVHDL_gigabit_ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
OS-X-LibMPSSE-SPI
Posts with mentions or reviews of OS-X-LibMPSSE-SPI.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
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Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
The chip also supports SPI and I2C though, but I have not tried that yet as it requires some more fiddling on the PC side regarding drivers (D2XX) and libraries (LibMPSSE). I figured that ethernet would provide the biggest bandwidth improvement, but it is considerably more complicated than the other options.
What are some alternatives?
When comparing hVHDL_gigabit_ethernet and OS-X-LibMPSSE-SPI you can also consider the following projects:
liteeth - Small footprint and configurable Ethernet core
ethernet - ethernet experiments on the ECP5-versa
verilog-ethernet - Verilog Ethernet components for FPGA implementation
Verilog_UDP_TCP - Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
axis_udp - This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
hVHDL_gigabit_ethernet vs liteeth
OS-X-LibMPSSE-SPI vs ethernet
hVHDL_gigabit_ethernet vs ethernet
OS-X-LibMPSSE-SPI vs verilog-ethernet
hVHDL_gigabit_ethernet vs Verilog_UDP_TCP
OS-X-LibMPSSE-SPI vs axis_udp
hVHDL_gigabit_ethernet vs verilog-ethernet
OS-X-LibMPSSE-SPI vs liteeth
hVHDL_gigabit_ethernet vs axis_udp