hVHDL_gigabit_ethernet
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers. (by hVHDL)
Verilog_UDP_TCP
Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý. (by ntpt7921)
| hVHDL_gigabit_ethernet | Verilog_UDP_TCP | |
|---|---|---|
| 1 | 1 | |
| 10 | 5 | |
| - | - | |
| 7.4 | 3.2 | |
| 9 months ago | over 2 years ago | |
| VHDL | Verilog | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hVHDL_gigabit_ethernet
Posts with mentions or reviews of hVHDL_gigabit_ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
Verilog_UDP_TCP
Posts with mentions or reviews of Verilog_UDP_TCP.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
-
Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
What are some alternatives?
When comparing hVHDL_gigabit_ethernet and Verilog_UDP_TCP you can also consider the following projects:
liteeth - Small footprint and configurable Ethernet core
axis_udp - This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
ethernet - ethernet experiments on the ECP5-versa
OS-X-LibMPSSE-SPI
verilog-ethernet - Verilog Ethernet components for FPGA implementation
hVHDL_gigabit_ethernet vs liteeth
Verilog_UDP_TCP vs axis_udp
hVHDL_gigabit_ethernet vs ethernet
Verilog_UDP_TCP vs ethernet
hVHDL_gigabit_ethernet vs OS-X-LibMPSSE-SPI
Verilog_UDP_TCP vs liteeth
hVHDL_gigabit_ethernet vs verilog-ethernet
Verilog_UDP_TCP vs verilog-ethernet
hVHDL_gigabit_ethernet vs axis_udp