icicle
32-bit RISC-V system on chip for iCE40 FPGAs (by grahamedgecombe)
fusesoc_template
Example of how to get started with olofk/fusesoc. (by sifferman)
| icicle | fusesoc_template | |
|---|---|---|
| 1 | 1 | |
| 284 | 12 | |
| - | - | |
| 6.0 | 1.8 | |
| 12 months ago | almost 3 years ago | |
| Python | Python | |
| ISC License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
icicle
Posts with mentions or reviews of icicle.
We have used some of these posts to build our list of alternatives
and similar projects.
-
"AMD Extends the UltraScale+ Product Portfolio"
If you just need a system to practice VHDL / Verilog on, the $50 entry point is a bit better. It won't be fast or big, but there's plenty to do and learn on something like that. The ICE40 is large enough to get a RISCV core for example.
fusesoc_template
Posts with mentions or reviews of fusesoc_template.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
What are some alternatives?
When comparing icicle and fusesoc_template you can also consider the following projects:
kianRiscV - RISC-V Linux SoC, marchID: 0x2b
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
edalize - An abstraction library for interfacing EDA tools