go-hdl
Hdl is a tool for easing the work with hardware description languages. (by m-kru)
serv
SERV - The SErial RISC-V CPU (by olofk)
go-hdl | serv | |
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2 | 20 | |
12 | 1,258 | |
- | - | |
0.0 | 7.6 | |
over 1 year ago | about 1 month ago | |
Go | Verilog | |
GNU General Public License v3.0 only | ISC License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
go-hdl
Posts with mentions or reviews of go-hdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-11.
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Code Checking for VHDL
I personally use 2 tools. The first one catches syntax errors, the second one can catch some logical errors. ghdl, thdl. The commands are respectively ghdl -s --std=08 path/to/file, thdl vet.
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Thdl - tool for easing the work with hardware description languages.
I have implemented the tool that some might find interesting https://github.com/m-kru/go-thdl. It is very similar in its concept to go. It allows vetting the code, seeing the documentation and generating the code (not yet supported). It uses simplified syntactic analysis, however it handles for example OSVVM and UVVM without any errors. Thanks to the simplified analysis the response is instant from human point of view. Currently only VHDL is supported, as this is my daily language, but adding support for example for SystemVerilog is foreseen.
serv
Posts with mentions or reviews of serv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-30.
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know