gem5
cs2410
gem5 | cs2410 | |
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3 | 1 | |
1,433 | 3 | |
4.5% | - | |
9.8 | 6.5 | |
about 16 hours ago | 12 months ago | |
C++ | C++ | |
BSD 3-clause "New" or "Revised" License | - |
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gem5
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Hot Chips 2023: Arm’s Neoverse V2
The idea is to write a C++ model that that produces cycle accurate outputs of the branch predictor, core pipeline, queues, memory latency, cache hierarchy, prefetch behaviour, etc. Transistor level accuracy isn't needed as long as the resulting cycle timings are identical or near identical. The improvement in workload runtime compared to a Verilog simulation is precisely because they aren't trying to model every transistor, but just the important parameters which effect performance.
Let's take a simple example: Instead of modeling a 64-bit adder in all its gory transistor level detail, you can just have the model return the correct data after 1 "cycle" or whatever your ALU latency is. As long as that cycle latency is the same as the real hardware, you'll get an accurate performance number.
What's particularly useful about these models is they enable much easier and faster state space exploration to see how a circuit would perform, well before going ahead with the Verilog implementation, which relatively speaking can take circuit designers ages. "How much faster would my CPU be if it had a 20% larger register file" can be answered in a day or two before getting a circuit designer to go try and implement such a thing.
If you want an open source example, take a look at the gem5 project (https://www.gem5.org). It's not quite as sophisticated as the proprietary models used in industry, but it's a used widely in academia and open source hardware design and is a great place to start.
- Custom Instructions: How do I go from MATCH/MASK to opcode?
cs2410
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Sophie Wilson. She designed the architecture behind your phone’s CPU. She is also a trans woman.
Here is a CPU simulator that I made during the Spring semester, which implements a subset of the RISC V ISA. :)
What are some alternatives?
renode - Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
qtrvsim - RISC-V CPU simulator for education purposes
riscv-none-elf-gcc-xpack - A binary xPack with the GNU RISC-V Embedded GCC toolchain with support of WCH RISCV CH56x... "WCH-Interrupt-fast"
ChampSim - ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
l4re-core - The core components of the L4Re operating system.
CHRONO - High-performance C++ library for multiphysics and multibody dynamics simulations
riscv-perf-model - Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model