fusesoc_template
prjxray
| fusesoc_template | prjxray | |
|---|---|---|
| 1 | 8 | |
| 12 | 740 | |
| - | 1.2% | |
| 1.8 | 8.4 | |
| almost 3 years ago | 10 days ago | |
| Python | Python | |
| - | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc_template
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Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
prjxray
- AMD Proposes an FPGA Subsystem User-Space Interface for Linux
- OpenPOWER Foundation Demoes the LibreBMC Power-Based Open-Source BMC
-
Using FPGAs for CyberSecurity/Cryptography.
There are many applications to FPGA security. You could use Project X-Ray to reverse engineer and edit a bitstream. You could learn how to use encrypted bitstreams to prevent someone from reverse engineering and editing your own bitstream. You could perform a side channel attack on an FPGA.
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NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptop (2019)
A bit of a nitpick - LiteX still needs Vivado installed for now for 7 series FPGAs. There's a project that's very far along in reverse engineering the Xilinx bitstream (https://github.com/f4pga/prjxray), but it's still missing many features (PCIe, SERDES, etc.).
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Partial reconfiguration safety problems
this information is not difficult to extract. maybe make a donation to https://github.com/f4pga/prjxray or appeal to their vanity. they can probably write such a script in an hour or two.
- Symbiflow: The GCC of the FPGA World
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The J1 Forth CPU
Here is a project to reverse engineer the Xilinx series 7 FPGAs to be able to target them with open source tools:
https://github.com/SymbiFlow/prjxray
What are some alternatives?
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
openFPGALoader - Universal utility for programming FPGA
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
FPGA-Ping-Pong-game - Simple Ping Pong game on Xilinx Spartan 3E
edalize - An abstraction library for interfacing EDA tools
f4pga - FOSS Flow For FPGA
litex - Build your hardware, easily!
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)