fpga-fft
DSP
| fpga-fft | DSP | |
|---|---|---|
| 1 | 1 | |
| 87 | 0 | |
| - | - | |
| 0.0 | 10.0 | |
| about 3 years ago | almost 2 years ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 or later | - |
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fpga-fft
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FPGA with DSP - which board and which FREE(!) software? 1M/s , 24bit FFT, FFT Ip?
Also, what is a small FFT for you? If I recall right the Xilinx FFT core is up to 2^16.. If you want to make a bigger FFT you need to divide it in little FFTs like this algorithm https://github.com/owocomm-0/fpga-fft
DSP
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Data not being processed by custom Verilog filtering module?
Right now I have a trapezoidal filter core (written in Verilog) created by a colleague that I know has been used with success in the past. So, starting from a simple ADC to DAC project provided by another Red Pitaya user, Pavel (here), I placed the core into the block design in between the ADC and DAC as such, let Vivado do its thing, and generated a bitstream without error (note that trap_0 has S00_AXIS data width 16, so it only takes the 16 LSB from the ADC, which I believe is from adc_dat_a_i). All of the source code for the trapezoidal filter core can be found on GitHub (top core and dependencies).
What are some alternatives?
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