find_first_set
OpenROAD
| find_first_set | OpenROAD | |
|---|---|---|
| 1 | 7 | |
| 1 | 1,334 | |
| - | 4.1% | |
| 0.0 | 10.0 | |
| over 2 years ago | 4 days ago | |
| Verilog | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
find_first_set
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How to compute log2 of non-constant logic variable?
I just had this problem. I made this O(logn) implementation: https://github.com/E4tHam/find_first_set
OpenROAD
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Importance of Open-Source EDA Tools for Academia
> [1]: https://theopenroadproject.org/
All it takes to check your point is to scroll down to the end and follow the link at the bottom of the page to the FOSSI foundation, who hosted this open letter, to realize that they have also developed some widely used EDA tools. Here's a link on case you have missed it
https://fossi-foundation.org/our-work/projects
- OpenROAD
- Ser programador científico en chile
- OpenROAD: Open IC Design Sythesis from Verilog
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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
If you're interested in tools, I highly recommend going through the (Google-supported) OpenROAD toolset - these guys are building up a open-source infrastructure for the full digital flow: https://theopenroadproject.org/ .
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VLSI Tools
You can have a quick look at OpenROAD. It is open source but will take sometime to get started with.
What are some alternatives?
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
OpenROAD-flow-scripts - OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
siliconcompiler - A modular build system for hardware
XiangShan - Open-source high-performance RISC-V processor
chisel-template - A template project for beginning new Chisel work
hammer - Hammer: Highly Agile Masks Made Effortlessly from RTL
caravel_fulgor_opamp - Test Chip General Purpose OpAmp using Skywater SKY130 PDK
tcl-opencl - Tcl extension for OpenCL
OpenSource-RoadMap-DataScience - ¡Camino a una educación autodidacta en Ciencia de Datos!
chisel-template - Chisel HDL Template Repository
FPGA-SDcard-Reader - An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。