ideas
Random ideas and interesting ideas for things we hope to eventually do. (by f4pga)
firrtl
Flexible Intermediate Representation for RTL (by chipsalliance)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ideas
Posts with mentions or reviews of ideas.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-12.
- FPGA Interchange format to enable interoperable FPGA tooling
-
CircuitPython: Programming Hardware in Python
See also the list from my low-level hardware description language unification idea[1]. There are mostly active projects.
[1] https://github.com/SymbiFlow/ideas/issues/19
firrtl
Posts with mentions or reviews of firrtl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-15.
- Firrtl – Flexible Intermediate Representation for RTL
-
FPGA Interchange format to enable interoperable FPGA tooling
Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl
-
Scala project (FIRRTL) failing to build on NixOS
I think the protoc comes from here?
What are some alternatives?
When comparing ideas and firrtl you can also consider the following projects:
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
python-fpga-interchange - Python interface to FPGA interchange format
netlistsvg - draws an SVG schematic from a JSON netlist
dotty - The Scala 3 compiler, also known as Dotty.
patchelf - A small utility to modify the dynamic linker and RPATH of ELF executables
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
chisel - Chisel: A Modern Hardware Design Language
firrtl - Flexible Intermediate Representation for RTL