ideas
python-fpga-interchange
| ideas | python-fpga-interchange | |
|---|---|---|
| 2 | 1 | |
| 86 | 39 | |
| - | - | |
| 0.0 | 0.0 | |
| about 2 years ago | over 1 year ago | |
| Python | ||
| - | ISC License |
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ideas
- FPGA Interchange format to enable interoperable FPGA tooling
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CircuitPython: Programming Hardware in Python
See also the list from my low-level hardware description language unification idea[1]. There are mostly active projects.
[1] https://github.com/SymbiFlow/ideas/issues/19
python-fpga-interchange
-
FPGA Interchange format to enable interoperable FPGA tooling
Or BLIF or EBLIF (already used by the verilog-to-routing flow). But no, let's invent yet another netlist format.
The fact that all of these existing formats are all named "xxx logic interchange format" should give you an idea what will happen to this new "interchange format".
From what I gather ( https://github.com/SymbiFlow/python-fpga-interchange/blob/ma... ) , the new format is basically the existing Yosys/nextpnr JSON format except dumped as a Cap'n Proto binary file.
I am absolutely not impressed.
I guess the meat here is on the universal device resources format, but this is not cool anyway.
What are some alternatives?
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
firrtl - Flexible Intermediate Representation for RTL
netlistsvg - draws an SVG schematic from a JSON netlist
chisel - Chisel: A Modern Hardware Design Language