corundum
Open source FPGA-based NIC and platform for in-network compute (by corundum)
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. (by JulianKemmerer)
| corundum | PipelineC | |
|---|---|---|
| 28 | 46 | |
| 1,468 | 542 | |
| 2.0% | - | |
| 9.4 | 9.5 | |
| 4 months ago | 6 days ago | |
| Verilog | Python | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
corundum
Posts with mentions or reviews of corundum.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-27.
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
PipelineC
Posts with mentions or reviews of PipelineC.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-03.
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
What are some alternatives?
When comparing corundum and PipelineC you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
pygears - HW Design: A Functional Approach
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
pycparser - :snake: Complete C99 parser in pure Python
litex - Build your hardware, easily!
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
hls4ml - Machine learning on FPGAs using HLS
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
antikernel - The Antikernel operating system project