corundum
NyuziProcessor
| corundum | NyuziProcessor | |
|---|---|---|
| 28 | 10 | |
| 1,468 | 1,916 | |
| 2.0% | - | |
| 9.4 | 3.4 | |
| 4 months ago | 7 days ago | |
| Verilog | C | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
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corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
NyuziProcessor
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Tiny GPU: A minimal GPU implementation in Verilog
Nice! I warmly encourage open-core GPU work.
Here's another: https://github.com/jbush001/NyuziProcessor
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FuryGpu – Custom PCIe FPGA GPU
There's also Nyuzi which is more GPGPU focused https://github.com/jbush001/NyuziProcessor, but the author also experimented with having it do 3D graphics.
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The WeeCee – Tiny Vortex86-Based DOS Gaming PC
You could probably layer a software implementation of the rasterization pipeline on top of a compute-focused open-source GPU architecture like Nyuzi: https://github.com/jbush001/NyuziProcessor/
I would expect a 2x slowdown over hardware rasterization, based on NVIDIA's work on such an approach, but this is probably fine if you're just trying to match Voodoo3 performance. And one could imagine bolting a minimal hardware rasterizer on top of Nyuzi to speed things up once the software implementation is working.
- FPGA as a GPU for Linux
- Nyuzi – An Experimental Open-Source FPGA GPGPU Processor
- An Experimental (Open-Source FPGA) GPGPU Processor called Nyuzi (by @jbush001)
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Exploring RustFFT's SIMD Architecture
Sounds like the Nyuzi processor :D
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
vdpau-va-driver-vp9 - Experimental VP9 codec support for vdpau-va-driver (NVIDIA VDPAU-VAAPI wrapper) and chromium-vaapi
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
openvga
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
TrellisBoard - Ultimate ECP5 development board
litex - Build your hardware, easily!
hardware - Verilog development and verification project for HOL4
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
ao486_MiSTer - ao486 port for MiSTer
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
OpenSimplex2 - C implementation for CPU and GPU of OpenSimplex 2