chisel
skywater-pdk
chisel | skywater-pdk | |
---|---|---|
25 | 27 | |
3,717 | 2,841 | |
1.1% | 1.0% | |
9.7 | 2.3 | |
8 days ago | 8 months ago | |
Scala | Python | |
Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
chisel
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Calyx: Intermediate Language for Hardware Accelerators
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
- Chisel: A Modern Hardware Design Language
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I may be creating an abomination
Inspired by Scala. Which can do a whole lot more, and worse. The currently biggest competitor to decades old hardware description languages is a Scala DSL.
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An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Already mentioned Chisel: https://www.chisel-lang.org/
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Trying to learn and work with FPGAs
I'm also a hobbyist. There are a number of alternative HDLs out there, and as hobbyists we can deviate more from the mainstream of (System)Verilog and VHDL if we desire, though you'll still need to be able to read them. In the past I've done Verilog, but lately I've been using SpinalHDL and have been really enjoying it. Its close relative Chisel also makes appearances in the RISC-V space.
- Alternate HDL language and Physical Design/EDA tools?
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Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
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Learning Verilog and FPGA
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
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If you keep clicking "Give 15 seconds" on Lichess, eventually it overflows to a negative number and you win
But some go further and ask "what if when we add a soldering station on top of it?"
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What universities have good PhD programmes in digital design?
In recent years Chisel HDL, RISC V, and SiFive came out of their architecture group, to name a few.
skywater-pdk
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Ask HN: Open-Source Simple CPU?
Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.
https://github.com/google/skywater-pdk
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Libre Silicon – Free semiconductors for everyone
It looks neat, but the process node is 1 um with 3 metal layers.
The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)
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Ask HN: How to start a fabless chip company targeting a modern process node?
From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup.
Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk
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Cadence Genus&Innovus
If you need a free PDK, check out: https://github.com/google/skywater-pdk
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DIY-Thermocam: The Affordable and Easy-to-Build Thermal Camera for Everyone
That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130.
https://github.com/google/skywater-pdk
One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.
https://www.digikey.com/en/products/detail/excelitas-technol...
One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it.
https://www.digikey.com/en/products/detail/panasonic-electro...
https://github.com/IdleHandsProject/diycamera (digiOBSCURA)
One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer
https://tinytapeout.com/
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Riscv board running quake II using a Radeon card.
Unlike x86_64 which can only legally be produced by two and one-quarter companies, RISC-V is a permissively open-sourced ISA so anyone can make a chip. Literally, you can download Verilog of Berkeley Rocket cores from Github and run it on an FPGA, or prep it to send to SkyWater to fab at 130nm.
- NCSU Free 45nmPDK
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Making open source hardware design a reality
Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk).
In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).
- Cadence market share?
- Compiling Code into Silicon
What are some alternatives?
SpinalHDL - Scala based HDL
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
myhdl - The MyHDL development repository
RocksDB - A library that provides an embeddable, persistent key-value store for fast storage.
amaranth - A modern hardware definition language and toolchain based on Python
gssi - Stuff I worked on while at GSSI (L'Aquila, Italy)
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
quibble - Quibble - the custom Windows bootloader
bsc - Bluespec Compiler (BSC)
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
circt - Circuit IR Compilers and Tools
Verilog.jl - Verilog for Julia