chisel-template
XiangShan
| chisel-template | XiangShan | |
|---|---|---|
| 1 | 32 | |
| 4 | 4,318 | |
| - | 1.2% | |
| 10.0 | 9.9 | |
| about 1 year ago | 6 days ago | |
| Scala | Scala | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
chisel-template
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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
Also it's not hard to start, there is a template provided by Chisel devs at https://github.com/freechipsproject/chisel-template or my own at https://github.com/carlosedp/chisel-template.
XiangShan
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Loongson 3A6000: A Star Among Chinese CPUs
Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.
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MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).
You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...
Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.
> Perhaps they will provide compiler patches if required.
I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...
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Ask HN: Are there any open source dual-issue RISC-V processor
This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan
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How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
Maybe implement a big feature for a open source design? like vroom or xiangshan.
- 大炼芯运动彻底破产，跪舔韩国要技术
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New processor, OS to propel open-source chip ecosystem
I did know about XiangShan, but not Aolai. Is it a Linux distribution?
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
- Open-source high-performance RISC-V processor
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
openc910 - OpenXuantie - OpenC910 Core
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
chisel-template - A template project for beginning new Chisel work
peakperf - Achieve peak performance on x86 CPUs and NVIDIA GPUs
chisel - Chisel: A Modern Hardware Design Language
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
cpufetch - Simple yet fancy CPU architecture fetching tool
kth - High performance Bitcoin development platform
vroom - VRoom! RISC-V CPU