ao486_MiSTer
chipyard
ao486_MiSTer | chipyard | |
---|---|---|
21 | 5 | |
236 | 1,432 | |
0.4% | 3.1% | |
5.8 | 9.7 | |
6 days ago | 3 days ago | |
Verilog | Scala | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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ao486_MiSTer
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Reverse engineering the Intel 386 processor's register cell
How about a 486 instead? :)
https://github.com/MiSTer-devel/ao486_MiSTer
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Issues with AO486
Have you checked all the details in https://github.com/MiSTer-devel/ao486_MiSTer ?
- Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
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Recently, I came across a video on Youtube by Linus Tech Tips about the PCEm emulator that I found to be cringy and ill-informed. As a computer engineer by education let me explain few core concepts on how emulation works.
You mention "Pentium MMX CPU" a few times in your post, but fail to mention any FPGA solution that can emulate a machine of that class. MiSTer can't do that, the best it can do is a 486 (not just missing MMX, doesn't even have an FPU).
- Exact 486 CPU Performance in Smallest Form Factor
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Emulate Any ISA Card With A Raspberry Pi And An FPGA
It has already happened: https://github.com/MiSTer-devel/ao486_MiSTer
- Are there FPGA cores for SB16/ET4KW32/NE2K?
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KEYBCS2
The last processor generation it worked on is the 486, but on a Pentium or newer it always fails with a “Debugging is not allowed” message.
I guessed the reason for that correctly - prefetch queue. Mentions of CUP386 in the comments also brought back more memories of the cracking scene in the late 80s/early 90s. There's some very interesting discussion on SMC vs CPU behaviour here --- in the context of an open-source 486-level SoC core:
https://github.com/MiSTer-devel/ao486_MiSTer/issues/33
chipyard
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Chisel: A Modern Hardware Design Language
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
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A repository that tracks upstream but allows separate tracking.
The repo in question is chipyard: https://github.com/ucb-bar/chipyard
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
- Chipyard: An Open Source RISC-V SoC Design Framework
- How to use a RISC V core for other purposes?
What are some alternatives?
dosbox-x - DOSBox-X fork of the DOSBox project
rocket-chip - Rocket Chip Generator
PCem-ROMs - This is a collection of requiered ROMs files for PCem emulator. RIP PCem 2021
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
elks - Embeddable Linux Kernel Subset - Linux for 8086
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
libi86 - Attempt to reimplement non-standard C library facilities (e.g. <conio.h>) used in MS-DOS programs, for IA-16 GCC & ACK ― mirror of https://gitlab.com/tkchia/libi86 • Ubuntu packages for cross-compilation at https://launchpad.net/%7Etkchia/+archive/ubuntu/build-ia16/ • DJGPP/MS-DOS binaries at https://github.com/tkchia/libi86/releases
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
NyuziProcessor - GPGPU microprocessor architecture
RVVM - The RISC-V Virtual Machine
vISA
nuclei-sdk - Nuclei RISC-V Software Development Kit