WARP_Core
Wilson AXI RISCV Processor Core (by AEW2015)
gateware
IP submodules, formatted for easier CI integration (by betrusted-io)
WARP_Core | gateware | |
---|---|---|
2 | 1 | |
7 | 25 | |
- | - | |
0.0 | 5.7 | |
almost 4 years ago | 5 months ago | |
VHDL | Verilog | |
- | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
WARP_Core
Posts with mentions or reviews of WARP_Core.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
gateware
Posts with mentions or reviews of gateware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
What are some alternatives?
When comparing WARP_Core and gateware you can also consider the following projects:
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
verilog-ethernet - Verilog Ethernet components for FPGA implementation
litex - Build your hardware, easily!
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
SpinalHDL - Scala based HDL
fiate - Fault Injection Automatic Test Equipment
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
WARP_Core vs soft_riscv
gateware vs verilog-ethernet
WARP_Core vs verilog-ethernet
gateware vs litex
WARP_Core vs SBusFPGA
gateware vs satcat5
WARP_Core vs SpinalHDL
gateware vs SBusFPGA
WARP_Core vs fiate
WARP_Core vs neorv32
WARP_Core vs satcat5
WARP_Core vs FPGA_RealTime_and_Static_Sobel_Edge_Detection