VHDL-Issues
myhdl
VHDL-Issues | myhdl | |
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11 | 15 | |
- | 1,006 | |
- | 1.2% | |
- | 5.1 | |
- | 3 months ago | |
Python | ||
- | GNU Lesser General Public License v3.0 only |
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VHDL-Issues
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What would be your go-to solution for configurable number of entity's output signals? (VHDL)
Not possible until VHDL 2019 using conditional analysis (basically VHDL pre-processor). This is supported by the newest intel Pro tools and most paid for simulators. A better version, without having to use conditional analysis, is proposed for VHDL 202X : https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/205
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How to create a register array in VHDL in which each entry in the array has input and outputting on the same cycle, behaves as a register, and is coded as an entry in an array?
You are confusing all sorts of VHDL terms. my_array is simply an array object, it has no ports. Ports exist on an entity. Vhdl has no direct knowledge of underlying hardware, hence register_array would not be suitable as a VHDL keyword. If you think it is, you need to suggest it at https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why are there only 3 languages for FPGA development?
For those who would like to see additional features / simplifications in VHDL, the working group accepts issues at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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A new suggested keyword register_array for VHDL
Reddit is not really a great place to suggest language modifications. The vhdl committee have a gitlab issues page where new language ideas can be submitted.. https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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sphinx-vhdl: Automatic generation of documentation from VHDL
See: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- Include I/O ports using parameter
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Active Busy VHDL Discussion Groups?
You too can contribute to the next revision of VHDL at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why is verilog more popular?
The IEEE WG welcomes new participants - especially people like yourself who have some experience. Got a good idea, you can interact with the VHDL WG community here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Signed Type vs Integer Type
If you want to get involved with language updates, we now use git issues. See here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- VHDL Standards and You ...
myhdl
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
Thank you for tackling this critical problem for logic designiners. I think the tools available are much too old for fast paced workflows.
From my experience attempting to get a similar workflow down for my company:
I tried to use verilator a while back but ultimately I couldn't because it didn't have same constraints in the verilog language features that I was going to use in production. It doesn't even matter who was missing a feature, verilator or the proprietary tool, it was just about getting them to be same that caused the cognitive dissonance that I didn't want to deal with.
I ultimately decided to move away from verilator and use the clunky proprietary tools since it was what would be used in production. Getting "verilator compatibility" seemed like a "nice to have".
Second, the a winning local-first framework of verilator wasn't really established. You show in your example running a test from the yaml file using what looks like a bash script. Even as an experienced programmer who knows bash and sh well, I still find it very hard to write complex thoughts in it. The last high level attempt I found to bridge this gap is likely https://www.myhdl.org/ I don't know them personally, but it seemed like they had some very good thoughts on what makes writing good hardware level tests good. I think it would be worth reaching out to them if you haven't already.
The one thing that even more critical was a way to run our tests locally. The 10-20 seconds it takes to start a docker image (best case) in the cloud is really frustrating when you are "so close to finding a bug" and you "just want to see if this one line change is going to fix it". Once we got our whole pipeline going, it would take 1-6 minutes to "start a run" since it often had to rebuild previous steps that cache large parts of the design.
So I think you will want to see how you can help bring people's "local's first" workflows slowly into the cloud. Some tools (or just tutorials) that help you take a failing test, and run it locally and on the cloud will be really good especially as you get people to transition!
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Why are there only 3 languages for FPGA development?
Also PyMTL, PyRTL, and MyHDL.
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Choice of Python HDL library
MyHDL
- Show HN: PyCircTools – Build digital circuits using Python
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
- Design Hardware with Python
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FPGA engineers specialize in DSP. What is your job? How much do you get paid? What is your work day like?
It is : https://www.myhdl.org/
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Compiling Code into Silicon
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.
[0]: https://www.myhdl.org/
[1]: https://github.com/lou1306/gssi/tree/master/2pc
- MyHDL open-source package for using Python as a hardware description
- GitHub - myhdl/myhdl: MyHDL is a free, open-source package for using Python as a hardware description and verification language.
What are some alternatives?
sphinx-vhdl
chisel - Chisel: A Modern Hardware Design Language
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
SpinalHDL - Scala based HDL
amaranth - A modern hardware definition language and toolchain based on Python
litex - Build your hardware, easily!
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
MicroPython - MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems