Silice
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines. (by sylefeb)
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux (by openhwgroup)
| Silice | cva6 | |
|---|---|---|
| 10 | 10 | |
| 1,244 | 2,100 | |
| - | 2.8% | |
| 9.2 | 9.7 | |
| 15 days ago | 5 days ago | |
| C++ | Assembly | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Silice
Posts with mentions or reviews of Silice.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-02-28.
-
Unreasonably effective – How video games use LUTs and how you can too
- how it is computed: https://github.com/sylefeb/Silice/blob/master/projects/ice-v...
Julia fractal, with a table to do integer multiply! (2.a.b = (a+b)^2 - a^2 - b^2, so just precompute all x^2 in a table! )
- Running Quake on an FPGA (Custom MRISC32 CPU) [video]
-
Another World Ported to FPGA
For anyone confused by the HDL, it's the authors custom language: https://github.com/sylefeb/Silice/tree/master
It provides a compiler to Verilog that then can be fed to traditional design flows.
-
An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Have a look at Silice, it's brilliant.
- FCCM'22 Tutorial: Recent Developments in Hardware Description Languages
- GitHub - sylefeb/Silice: Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
- Silice: A language for hardcoding Algorithms into FPGA hardware
-
The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
I was more interested in the Silice project above:
https://github.com/sylefeb/Silice/tree/draft
-
How to contribute to open source?
I'm an intern at a french IT lab and my boss is working on an open-source FPGA language, you might want to check it out https://github.com/sylefeb/Silice .
cva6
Posts with mentions or reviews of cva6.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
-
Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
-
Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
-
Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
-
Some data points on Vivado performance on Ryzen and Alder Lake
I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6
-
What is Purism's roadmap for open-source hardware/schematics?
When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.
-
XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
-
How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
-
OpenHW Group and Mitacs announce a $22.5M research program for open-source processors
Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.
What are some alternatives?
When comparing Silice and cva6 you can also consider the following projects:
hls4ml - Machine learning on FPGAs using HLS
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
chisel-book - Digital Design with Chisel
litex - Build your hardware, easily!
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
verilator - Verilator open-source SystemVerilog simulator and lint system
karuta - Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
openFPGALoader - Universal utility for programming FPGA
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
a5k - Another World on a chip
litedram - Small footprint and configurable DRAM core