Silice
PipelineC
| Silice | PipelineC | |
|---|---|---|
| 10 | 46 | |
| 1,230 | 542 | |
| - | - | |
| 9.2 | 9.5 | |
| 5 days ago | 5 days ago | |
| C++ | Python | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Silice
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Unreasonably effective – How video games use LUTs and how you can too
- how it is computed: https://github.com/sylefeb/Silice/blob/master/projects/ice-v...
Julia fractal, with a table to do integer multiply! (2.a.b = (a+b)^2 - a^2 - b^2, so just precompute all x^2 in a table! )
- Running Quake on an FPGA (Custom MRISC32 CPU) [video]
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Another World Ported to FPGA
For anyone confused by the HDL, it's the authors custom language: https://github.com/sylefeb/Silice/tree/master
It provides a compiler to Verilog that then can be fed to traditional design flows.
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An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Have a look at Silice, it's brilliant.
- FCCM'22 Tutorial: Recent Developments in Hardware Description Languages
- GitHub - sylefeb/Silice: Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
- Silice: A language for hardcoding Algorithms into FPGA hardware
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The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
I was more interested in the Silice project above:
https://github.com/sylefeb/Silice/tree/draft
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How to contribute to open source?
I'm an intern at a french IT lab and my boss is working on an open-source FPGA language, you might want to check it out https://github.com/sylefeb/Silice .
PipelineC
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PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
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What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
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What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
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Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
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Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
What are some alternatives?
hls4ml - Machine learning on FPGAs using HLS
pygears - HW Design: A Functional Approach
chisel-book - Digital Design with Chisel
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
karuta - Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
pycparser - :snake: Complete C99 parser in pure Python
openFPGALoader - Universal utility for programming FPGA
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
a5k - Another World on a chip
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
antikernel - The Antikernel operating system project