SDRAM_Controller_Verilog
hdl
| SDRAM_Controller_Verilog | hdl | |
|---|---|---|
| - | 5 | |
| 4 | 1,378 | |
| - | 2.0% | |
| 0.0 | 9.1 | |
| about 3 years ago | 7 days ago | |
| Verilog | Verilog | |
| - | GNU General Public License v3.0 or later |
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SDRAM_Controller_Verilog
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Tracking mentions began in Dec 2020.
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
uhd - The USRP™ Hardware Driver Repository
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.