Rudi-RV32I VS vivado-risc-v

Compare Rudi-RV32I vs vivado-risc-v and see what are their differences.

Rudi-RV32I

A rudimental RISCV CPU supporting RV32I instructions, in VHDL (by hamsternz)

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro (by eugene-tarassov)
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Rudi-RV32I vivado-risc-v
7 6
106 738
- -
0.0 7.5
over 3 years ago 3 days ago
VHDL Tcl
MIT License -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Rudi-RV32I

Posts with mentions or reviews of Rudi-RV32I. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-01-10.

vivado-risc-v

Posts with mentions or reviews of vivado-risc-v. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.
  • Recommendations for RISC-V on FPGA
    7 projects | /r/FPGA | 8 Mar 2023
    Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
  • How can I learn about RISC-V and use case? I want to do a project for begginers
    2 projects | /r/FPGA | 5 Feb 2023
  • Open-source RISC-V CPU projects for contribution
    8 projects | /r/RISCV | 28 Jan 2023
    For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v
  • can one run one a linux distro like debian on an fpga?
    1 project | /r/FPGA | 9 Nov 2022
    I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?
  • Error when preparing a USB for use with an FPGA
    1 project | /r/Ubuntu | 22 Mar 2022
  • Running Hello World on a bare-metal RISC-V FPGA
    3 projects | /r/RISCV | 10 Jan 2022
    But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.

What are some alternatives?

When comparing Rudi-RV32I and vivado-risc-v you can also consider the following projects:

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

wb2axip - Bus bridges and other odds and ends

rocket-chip - Rocket Chip Generator

nybbleForth - Stack machine with 4-bit instructions

neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces

mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.

autofpga - A utility for Composing FPGA designs from Peripherals

riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine