Rudi-RV32I
vivado-risc-v
Rudi-RV32I | vivado-risc-v | |
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7 | 6 | |
106 | 738 | |
- | - | |
0.0 | 7.5 | |
over 3 years ago | 3 days ago | |
VHDL | Tcl | |
MIT License | - |
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Rudi-RV32I
- Input Output For a custom CPU
- Requesting an existing Design Specification Sheet for a Single Cycle RISC-V processor design
- IMPLEMENTING RISC-V BASED PROCESSOR
- GUIDANCE NEEDED
- Running Hello World on a bare-metal RISC-V FPGA
- Nand2Tetris: can anyone give me a deeper insight about the ALU chip?
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CPU DESIGN
Here was my first attempt at a RV32I design, https://github.com/hamsternz/Rudi-RV32I
vivado-risc-v
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- How can I learn about RISC-V and use case? I want to do a project for begginers
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Open-source RISC-V CPU projects for contribution
For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v
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can one run one a linux distro like debian on an fpga?
I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?
- Error when preparing a USB for use with an FPGA
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Running Hello World on a bare-metal RISC-V FPGA
But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
wb2axip - Bus bridges and other odds and ends
rocket-chip - Rocket Chip Generator
nybbleForth - Stack machine with 4-bit instructions
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.
autofpga - A utility for Composing FPGA designs from Peripherals
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine