OsvvmLibraries
cocotb
| OsvvmLibraries | cocotb | |
|---|---|---|
| 2 | 28 | |
| 46 | 1,607 | |
| - | 2.4% | |
| 8.0 | 9.7 | |
| 24 days ago | 4 days ago | |
| QMake | Python | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OsvvmLibraries
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
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Comments and rants about tools, and a crazy idea
For building simulation projects, you might consider OSVVM. See: https://github.com/OSVVM/OsvvmLibraries
cocotb
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Designing a Low Latency 10G Ethernet Core
The use of cocotb and pyuvm for verification
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How is Python used in test automation in embedded systems?
For FPGA/HDL work, there's cocotb
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Introducing CoHDL
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
- Use cocotb to test and verify chip designs in Python
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Trying to learn and work with FPGAs
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
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Help understanding how this makefile works?
I know it might be difficult without much context, but this makefile is called by a top level makefile. very confused if lines 35-74 do anything. They seem to be a mix of real makefile syntax and just straight up comments. what do these lines do?
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COBS protocol decoder progress
Learn more about this here: https://www.cocotb.org/
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AXI-Stream meme
Also consider cocotb, this thread has some compelling arguments. I'd say as a student, learning industry tools isn't necessarily the best thing you could spend your time on. Getting fast at design AND verification, where you can maintain flow state and run better microexperiments means you will understand more, faster.
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cocotb
Have you tried looking at the mixed language example?
- We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
cocotbext-axi - AXI interface modules for Cocotb
Documentation - OSVVM Documentation
cocotb-test - Unit testing for cocotb
viv-prj-gen - tcl scripts used to build or generate vivado projects automatically
amaranth - A modern hardware definition language and toolchain based on Python
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
chiselverify - A dynamic verification library for Chisel.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
SpinalHDL - Scala based HDL
chisel - Chisel: A Modern Hardware Design Language
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development