OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology. (by SparcLab)
OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130 (by AngeloJacobo)
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| OpenSERDES | OpenLANE-Sky130-Physical-Design-Workshop | |
|---|---|---|
| 1 | 1 | |
| 115 | 32 | |
| - | - | |
| 10.0 | 10.0 | |
| about 2 years ago | over 1 year ago | |
| Verilog | ||
| GNU General Public License v3.0 only | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenSERDES
Posts with mentions or reviews of OpenSERDES.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-14.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
But here is an open source ASIC-proven serdes block, [OpenSERDES](https://github.com/SparcLab/OpenSERDES). [Here's the paper describing it](https://arxiv.org/abs/2105.13256). It's only 2 Gb/s per link, but it seems like that would be enough to do DDR3. It is available on Skywater OpenPDK 130nm.
OpenLANE-Sky130-Physical-Design-Workshop
Posts with mentions or reviews of OpenLANE-Sky130-Physical-Design-Workshop.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Documentation for the Workshop: Advanced Physical Design using OpenLane/Sky130
Hi, here is a compilation of my notes for the 5 day workshop: Advanced Physical Design using OpenLANE/Sky130 by VSD back in August. The goal of that workshop is to cover the complete RTL2GDSII flow using the open-source flow OpenLane with the SKY130nm PDK.
What are some alternatives?
When comparing OpenSERDES and OpenLANE-Sky130-Physical-Design-Workshop you can also consider the following projects:
sirdez - Glorious Binary Serialization and Deserialization for TypeScript.
sky90fd-pdk
BlueCap - iOS Bluetooth LE framework
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
litex - Build your hardware, easily!
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
litedram - Small footprint and configurable DRAM core
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
OpenSERDES vs sirdez
OpenLANE-Sky130-Physical-Design-Workshop vs sky90fd-pdk
OpenSERDES vs BlueCap
OpenLANE-Sky130-Physical-Design-Workshop vs riscv-cores-list
OpenSERDES vs litex
OpenLANE-Sky130-Physical-Design-Workshop vs openlane
OpenSERDES vs litedram
OpenLANE-Sky130-Physical-Design-Workshop vs riscv-cores-list
OpenSERDES vs VexRiscv
OpenLANE-Sky130-Physical-Design-Workshop vs OpenTimer