FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s (by AngeloJacobo)
SDRAM_Controller_Verilog
This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz. (by RichardPar)
| FPGA_SDRAM_Controller | SDRAM_Controller_Verilog | |
|---|---|---|
| 1 | - | |
| 19 | 4 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | about 3 years ago | |
| Verilog | Verilog | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_SDRAM_Controller
Posts with mentions or reviews of FPGA_SDRAM_Controller.
We have used some of these posts to build our list of alternatives
and similar projects.
SDRAM_Controller_Verilog
Posts with mentions or reviews of SDRAM_Controller_Verilog.
We have used some of these posts to build our list of alternatives
and similar projects.
We haven't tracked posts mentioning SDRAM_Controller_Verilog yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
When comparing FPGA_SDRAM_Controller and SDRAM_Controller_Verilog you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
hdl - HDL libraries and projects
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!