ChampSim
qtrvsim
ChampSim | qtrvsim | |
---|---|---|
2 | 1 | |
442 | 428 | |
4.3% | 7.7% | |
7.3 | 8.9 | |
12 days ago | 8 days ago | |
C++ | C++ | |
Apache License 2.0 | GNU General Public License v3.0 only |
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ChampSim
qtrvsim
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How a CPU works: Bare metal C on my RISC-V toy CPU
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu
What are some alternatives?
Kite - Kite: Architecture Simulator for RISC-V Instruction Set
Astro8-Computer - Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
cs2410 - An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
fpga-experiments
risc-v_pipelined_cpu - RISC-V CPU with a 5-stage pipeline, written in SystemVerilog
Digital - A digital logic designer and circuit simulator.
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA