BYU_PYNQ_PR_Video_Pipeline_Hardware
BYU Pynq PR Video Pipeline Hardware (by byuccl)
xfcp
Extensible FPGA control platform (by alexforencich)
Our great sponsors
BYU_PYNQ_PR_Video_Pipeline_Hardware | xfcp | |
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2 | 5 | |
7 | 51 | |
- | - | |
0.0 | 0.0 | |
over 4 years ago | about 1 year ago | |
VHDL | Verilog | |
- | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
BYU_PYNQ_PR_Video_Pipeline_Hardware
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline_Hardware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
xfcp
Posts with mentions or reviews of xfcp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
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Ethernet PC-FPGA interface
This is exactly what I created https://github.com/alexforencich/xfcp for - Ethernet and serial to multiple internal components, with the ability to enumerate said components.
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Options for control and configuration of FPGA from PC
This is basically what I made XFCP for: https://github.com/alexforencich/xfcp
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .
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FPGA development live stream: FPGA board bring-up and testing of high-speed serializers
I'll use my XFCP project to interface with the FPGA from Python via a USB serial chip. This provides access to the I2C bus on the board, for configuring the PLL chips and interfacing with the QSFP28 optical transceivers. Additionally, it connects to the dynamic reconfiguration ports (DRP) on the GTY transceivers, and I'll use that for performing BER measurements at 25 Gbps through a handful of QSFP28 cables and optical modules. It looks like I might also have to do some fine-tuning of some of the analog parameters on the transceivers (namely pre-emphasis).
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FPGA development live stream: FPGA board bring-up and testing
I recently acquired a pair of rather large FPGA boards that have a bunch of high-speed IO. I figure it might be interesting to show the process for bringing them up in terms of the reference clock generation and distribution components on the board for the high-speed serializers, as well as performing some simple sanity checks (BER testing) on all of the interfaces to make sure everything is operational. I'll use my XFCP project to interface with the FPGA from Python for configuring the clocking components over I2C and for performing the BER measurements on the GTY transceivers via DRP.
What are some alternatives?
When comparing BYU_PYNQ_PR_Video_Pipeline_Hardware and xfcp you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
SpinalHDL - Scala based HDL
litex - Build your hardware, easily!
WARP_Core - Wilson AXI RISCV Processor Core
corundum - Open source FPGA-based NIC and platform for in-network compute
verilog-wishbone - Verilog wishbone components
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-ethernet
xfcp vs SBusFPGA
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SpinalHDL
xfcp vs litex
BYU_PYNQ_PR_Video_Pipeline_Hardware vs WARP_Core
xfcp vs verilog-ethernet
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SBusFPGA
xfcp vs corundum
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-wishbone
xfcp vs SpinalHDL
BYU_PYNQ_PR_Video_Pipeline_Hardware vs satcat5
xfcp vs satcat5